Sub-20 ps high-speed ECL bipolar transistor with low parasitic architecture

Author

Iinuma, Toshihiko ; Itoh, Nobuyuki ; Nakajima, Hiroomi ; Inou, Kazumi ; Matsuda, Satoshi ; Yoshino, Chihiro ; Tsuboi, Yoshiroh ; Katsumata, Yasuhiro ; Iwai, Hisato

Author_Institution

ULSI Res. Center, Toshiba Corp., Kawasaki, Japan

Volume

42

Issue

3

fYear

1995

fDate

3/1/1995 12:00:00 AM

Firstpage

399

Lastpage

405

Abstract

Reducing parasitic capacitance and resistance is an effective means of both improving ECL gate delay and increasing f_T values. In this paper, we demonstrate a device with sub-20 ps t_pd values even at f_T=23 GHz, a performance which has been achieved by implementing a number of techniques. These include 1) low-stress deep- and shallow-trench isolation to reduce C_CB, 2) a low-concentration collector design to reduce C_CB, 3) NiSi-salicided base and emitter electrodes to reduce R_B, and 4) a shallow base formed by double diffusion technology for relatively high f_T with a low-concentration collector design. The low-concentration collector design gives the device a high breakdown voltage of 6.2 V

Keywords

bipolar transistors; emitter-coupled logic; isolation technology; semiconductor technology; 20 ps; 23 GHz; 6.2 V; NiSi-Si; NiSi-salicided base electrodes; NiSi-salicided emitter electrodes; breakdown voltage; cut off frequency; double diffusion technology; gate delay; high-speed ECL bipolar transistor; low-concentration collector design; low-stress deep-trench isolation; low-stress shallow-trench isolation; parasitic capacitance; parasitic resistance; shallow base; Bipolar transistors; Cutoff frequency; Delay effects; Electrodes; Epitaxial growth; Germanium silicon alloys; Parasitic capacitance; Roentgenium; Senior members; Silicon germanium;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.368035

Filename

368035