Title :
Architecture-level performance estimation method based on system-level profiling
Author :
Ueda, K. ; Sakanushi, K. ; Takeuchi, Y. ; Imai, M.
Author_Institution :
Graduate Sch. of Inf. Sci. & Technol., Osaka Univ., Japan
Abstract :
An architecture-level performance estimation method based on system-level profiling is proposed. The proposed method estimates the performance of the target architecture by the following procedures: system-level profiling; automatic construction of the execution order graph and execution dependency graph from the profiling information; and estimation of the system performance based on the graph analysis. The proposed method enables fast performance estimation because it can estimate the performance of various architectures from the same system-level profiling information. Experimental results show that the proposed estimation method is 2700 times faster than the architecture-level simulation.
Keywords :
computer architecture; graph theory; performance evaluation; architecture-level performance estimation; automatic graph construction; execution dependency graph; execution order graph; fast performance estimation; graph analysis; system-level profiling;
Journal_Title :
Computers and Digital Techniques, IEE Proceedings -
DOI :
10.1049/ip-cdt:20045057