Title :
High-performance arithmetic coding VLSI macro for the H264 video compression standard
Author :
Núñez, J.L. ; Chouliaras, V.A.
Author_Institution :
Dept. of Electron. & Electr. Eng., Bristol Univ., UK
Abstract :
This paper investigates the algorithmic complexity of arithmetic coding in the new H264 video coding standard and proposes a processor-coprocessor architecture to reduce it by more than an order of magnitude. The proposed coprocessor is based on an innovative algorithm known as the MZ-coder and maintains the original coding efficiency via a low-complexity, multiplication-free, non-stalling, fully pipelined architecture. The coprocessor achieves a constant throughput for both coding and decoding processes of 1 symbol per cycle and is designed to be attached to a controlling embedded RISC CPU whose instruction set has been extended with arithmetic coding instructions.
Keywords :
VLSI; arithmetic codes; code standards; computational complexity; coprocessors; data compression; pipeline processing; video codecs; video coding; H264 video compression standard; MZ-coder; algorithmic complexity; arithmetic coding; high-performance arithmetic coding VLSI macro; processor-coprocessor architecture; Arithmetic; CMOS technology; Central Processing Unit; Code standards; Computational efficiency; Coprocessors; Personal digital assistants; Very large scale integration; Video coding; Video compression;
Journal_Title :
Consumer Electronics, IEEE Transactions on
DOI :
10.1109/TCE.2005.1405712