DocumentCode :
1247233
Title :
An algorithm for nanopipelining of RTD-based circuits and architectures
Author :
Gupta, Pallav ; Jha, Niraj K.
Author_Institution :
Dept. of Electr. Eng., Princeton Univ., NJ, USA
Volume :
4
Issue :
2
fYear :
2005
fDate :
3/1/2005 12:00:00 AM
Firstpage :
159
Lastpage :
167
Abstract :
In this study, an algorithm to postprocess a register-transfer-level architecture to enable gate-level pipelining or nanopipelining is presented. Nanopipelining is well suited for the nanotechnology based on resonant-tunneling diodes (RTDs) and offers the opportunity to obtain massive throughput and, therefore, has applications in data-intensive algorithms such as digital signal processing. Since RTDs are a self-latching nanoscale device, nanopipelining is an implicit property that should be exploited for this technology. This study explores and addresses the benefits of nanopipelining and presents an algorithm for architectural nanopipelining.
Keywords :
nanoelectronics; parallel architectures; pipeline arithmetic; resonant tunnelling diodes; threshold logic; RTD circuits; data intensive algorithms; digital signal processing; nanopipelining; nanotechnology; register transfer level architecture; resonant tunneling diodes; self latching nanoscale device; CMOS technology; Computer architecture; HEMTs; Logic circuits; MODFETs; Nanoscale devices; Nanotechnology; Resonant tunneling devices; Semiconductor diodes; Signal processing algorithms; Nanopipelining; RTD-based circuits and architectures; nanotechnology; resonant-tunneling diodes (RTDs);
fLanguage :
English
Journal_Title :
Nanotechnology, IEEE Transactions on
Publisher :
ieee
ISSN :
1536-125X
Type :
jour
DOI :
10.1109/TNANO.2004.842069
Filename :
1405992
Link To Document :
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