• DocumentCode
    1247245
  • Title

    Nonphotolithographic nanoscale memory density prospects

  • Author

    DeHon, André ; Goldstein, Seth Copen ; Kuekes, Philip J. ; Lincoln, Patrick

  • Author_Institution
    Comput. Sci. Dept., California Inst. of Technol., Pasadena, CA, USA
  • Volume
    4
  • Issue
    2
  • fYear
    2005
  • fDate
    3/1/2005 12:00:00 AM
  • Firstpage
    215
  • Lastpage
    228
  • Abstract
    Technologies are now emerging to construct molecular-scale electronic wires and switches using bottom-up self-assembly. This opens the possibility of constructing nanoscale circuits and memories where active devices are just a few nanometers square and wire pitches may be on the order of ten nanometers. The features can be defined at this scale without using photolithography. The available assembly techniques have relatively high defect rates compared to conventional lithographic integrated circuits and can only produce very regular structures. Nonetheless, with proper memory organization, it is reasonable to expect these technologies to provide memory densities in excess of 1011 b/cm2 with modest active power requirements under 0.6 W/Tb/s for random read operations.
  • Keywords
    molecular electronics; nanoelectronics; nanolithography; nanowires; self-assembly; storage management; switches; high defect rate; memory densities; memory organization; molecular scale electronic wires; nanoscale circuits; nonphotolithographic nanoscale memory density prospects; photolithography; power requirement; self-assembly; switches; wire pitches; Circuits; Computer science; Hysteresis; Laboratories; Lithography; Nanoscale devices; Nonvolatile memory; Self-assembly; Switches; Wires; Defect tolerance; electronic nanotechnology; memory density; memory organization; molecular electronics;
  • fLanguage
    English
  • Journal_Title
    Nanotechnology, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1536-125X
  • Type

    jour

  • DOI
    10.1109/TNANO.2004.837849
  • Filename
    1405998