Accurate and efficient simulation of synchronous digital switching noise in systems on a chip

A new method is presented to compress switching information in large synchronous digital circuits. This is combined with an efficient generation of digital cell library noise signatures and results in an accurate estimation of the switching noise in digital circuits. It provides a practical approach to generating the digital switching noise for simulating substrate coupling noise in mixed-signal ICs. Nearly two orders of magnitude reduction in the memory and simulation time are achieved using this approach without significant loss of accuracy.