Title :
4-bit adder-accumulator at 41-GHz clock frequency in InP DHBT technology
Author :
Turner, Steven Eugene ; Elder, Richard B., Jr. ; Jansen, Douglas S. ; Kotecki, David E.
Author_Institution :
Univ. of Maine, Orono, ME, USA
fDate :
3/1/2005 12:00:00 AM
Abstract :
A 41-GHz 4-b adder-accumulator test circuit implemented in InP double heterojunction bipolar transistor (DHBT) technology using 624 transistors is reported. High clock rates are obtained by combining the logic functions into pipelined latches. The adder-accumulator contains a single-level parallel-gated carry circuit that is used as a step toward reduced power consumption. The carry circuit has a maximum clock frequency of 55 GHz. The accumulator architecture employs modular, pipelined 2-b adders and is cascadable to 2 N-bits. The test circuit includes a 4-b digital to analog converter (DAC) that facilitates demonstration of high-speed operation.
Keywords :
III-V semiconductors; adders; bipolar logic circuits; carry logic; clocks; digital-analogue conversion; heterojunction bipolar transistors; indium compounds; logic design; pipeline processing; 4 bits; 41 GHz; 55 GHz; DHBT technology; InP; accumulator architecture; adder-accumulator test circuit; clock frequency; digital-to-analog converter; double heterojunction bipolar transistor; frequency divider; high clock rates; high-speed integrated circuits; logic functions; pipelined latches; power consumption; single-level parallel-gated carry circuit; Bipolar transistor circuits; Circuit testing; Clocks; DH-HEMTs; Double heterojunction bipolar transistors; Energy consumption; Frequency; Indium phosphide; Latches; Logic functions; Accumulator; adder; carry; frequency divider; heterojunction bipolar transistor (HBT); high-speed integrated circuits; indium phosphide (InP);
Journal_Title :
Microwave and Wireless Components Letters, IEEE
DOI :
10.1109/LMWC.2005.844199
