DocumentCode :
1247355
Title :
High-speed demonstration of single-flux-quantum cross-bar switch up to 50 GHz
Author :
Kameda, Yoshio ; Yorozu, Shinichi ; Hashimoto, Yoshihito ; Terai, Hirotaka ; Fujimaki, Akira ; Yoshikawa, Nobuyuki
Author_Institution :
Supercond. Res. Lab., ISTEC, Ibaraki, Japan
Volume :
15
Issue :
1
fYear :
2005
fDate :
3/1/2005 12:00:00 AM
Firstpage :
6
Lastpage :
10
Abstract :
We have been developing a single-flux-quantum (SFQ) cross-bar switch, which is a main component of a network packet switch. We think that a network switch is an application in which the high speed of SFQ technology would be advantageous. Anticipating general and large-scale SFQ logic circuit design, we used the cell-based design method and the CONNECT standard SFQ cell library. The two-input and two-output cross-bar switch, a core switch component, consists of 13 logic cells connected by Josephson-transmission-line (JTL) cells. Because of the large size of JTL cells and the large delay in them, timing adjustment becomes more difficult as the operating speed and circuit size increase. After using a commercially available automatic router to find appropriate routes efficiently, we used a static timing analyzer for fine timing adjustment. Timing violations were fixed by changing JTL path delays using the tools we developed. The target operating frequency of the switch was 40 GHz, which corresponds to a clock period of 25 ps. Careful timing adjustment was necessary to ensure correct operations at such a high speed. The test chip was fabricated by using an NEC standard Nb process. The circuit, including on-chip test circuitry, was composed of about 1500 Josephson junctions. We confirmed its correct operations up to 50 GHz with a bias margin of ±20%.
Keywords :
logic design; superconducting logic circuits; switches; 40 GHz; CONNECT standard SFQ cell library; JTL path delays; Josephson junctions; Josephson-transmission-line cells; NEC standard Nb process; SFQ logic circuit design; SFQ technology; automatic router; cell-based design method; core switch component; fine timing adjustment; logic cells; network packet switch; on-chip test circuitry; single-flux-quantum cross-bar switch; static timing analyzer; timing violations; Circuit testing; Delay; Design methodology; Josephson junctions; Large-scale systems; Libraries; Logic circuits; Packet switching; Switches; Timing; Cell-based design; logic circuit; single-flux-quantum (SFQ) circuit; timing analysis;
fLanguage :
English
Journal_Title :
Applied Superconductivity, IEEE Transactions on
Publisher :
ieee
ISSN :
1051-8223
Type :
jour
DOI :
10.1109/TASC.2004.839771
Filename :
1406081
Link To Document :
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