Voltage and Return Plane Bounce Affecting Digital Components Using Different Printed Circuit Board Edge Termination Methodologies

This paper illustrates effects of board edge termination related to development of either voltage or return plane bounce exceeding operational margin levels of digital components at multiple locations within a printed circuit board (PCB). We study an actual problem encountered by design engineers using a worse-case configuration. This paper also explains how power and/or return bounce is developed. Lack of optimal plane termination at the physical edges of a PCB will exacerbate plane bounce. In addition, a solution that prevents this problem is provided in Section VIII.