• DocumentCode
    1248609
  • Title

    A 107.4 dB SNR Multi-Bit Sigma Delta ADC With 1-PPM THD at - 0.12 dB From Full Scale Input

  • Author

    Wu, Jian-Yi ; Zhang, Zhenyong ; Subramoniam, Rajaram ; Maloberti, Franco

  • Author_Institution
    Nat. Semicond. Labs., Santa Clara, CA, USA
  • Volume
    44
  • Issue
    11
  • fYear
    2009
  • Firstpage
    3060
  • Lastpage
    3066
  • Abstract
    A second order sigma delta modulator (SDM) with a 5-bit quantizer has been presented using several novel techniques: simplified DAC arrays for easy implementation, high-order truncation noise shaping for increased tolerance to analog imperfections, and an extended dynamic range for a maximum input signal swing of up to -0.12 dBFS (Full Scale). With truncation filters and a pseudo SDM in the DSP, the truncation and saturation errors are compensated through the DAC arrays and the DSP. The design, fabricated in a 0.18 mum dual gate oxide (DGO) process obtains a signal-to-noise-and-distortion ratio (SNDR) of 105.9 dB and a dynamic range (DR) of 107.4 dB with 31.25-KHz bandwidth at an 8-MHz sampling frequency and a power consumption of 14.7 mW.
  • Keywords
    analogue-digital conversion; sigma-delta modulation; DAC arrays; bandwidth 31.25 kHz; dual gate oxide; frequency 8 MHz; high-order truncation noise shaping; multibit sigma delta ADC; power 14.7 mW; second order sigma delta modulator; signal-to-noise-and-distortion ratio; size 0.18 mum; truncation filters; Bandwidth; Delta modulation; Delta-sigma modulation; Digital signal processing; Dynamic range; Filters; Noise shaping; Signal design; Signal processing; Signal sampling; DAC with level reduction; delta sigma ADC; extended dynamic range; truncation noise cancellation;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.2009.2032753
  • Filename
    5308732