DVLASIC: catastrophic fault yield simulation in a distributed processing environment

Simulation of local process disturbances is a computationally intensive task. The VLASIC (VLSI LAyout Simulation for Integrated Circuits) catastrophic-fault yield simulator uses a Monte Carlo method that often requires tens of CPU hours to perform a simulation. In order to reduce the simulation time, DVLASIC, the distributed-environment version developed by the authors, achieves a speedup of 13.3 over VLASIC, with an efficiency of 89%. The authors describe the distributed processing environment and implementation techniques used to obtain this speedup. The distributed processing environment can also be applied to many other CAD problems