DocumentCode :
1249333
Title :
High-speed parallel Viterbi decoding: algorithm and VLSI-architecture
Author :
Fettweis, Gerhard ; Meyr, Heinrich
Author_Institution :
IBM Almaden Res. Center, San Jose, CA, USA
Volume :
29
Issue :
5
fYear :
1991
fDate :
5/1/1991 12:00:00 AM
Firstpage :
46
Lastpage :
55
Abstract :
The Viterbi algorithm (VA) is considered as an example of a fairly complex algorithm that needs to be implemented for high-speed applications. A brief introduction to the algorithm is given, and the state of the art of high-speed Viterbi decoders is reviewed. The three principal levels of introducing additional parallelism into an algorithm-bit level, word level, and algorithm level-are outlined, and a solution for the VA at the bit level is indicated.<>
Keywords :
VLSI; decoding; parallel algorithms; parallel architectures; VLSI architecture; Viterbi algorithm; algorithm level; bit level; high-speed Viterbi decoders; parallel Viterbi decoding; parallel algorithm; word level; Application specific integrated circuits; CMOS logic circuits; CMOS technology; Clocks; Decoding; Frequency; Gallium arsenide; Pipeline processing; Signal processing algorithms; Viterbi algorithm;
fLanguage :
English
Journal_Title :
Communications Magazine, IEEE
Publisher :
ieee
ISSN :
0163-6804
Type :
jour
DOI :
10.1109/35.79382
Filename :
79382
Link To Document :
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