Title :
High-speed parallel Viterbi decoding: algorithm and VLSI-architecture
Author :
Fettweis, Gerhard ; Meyr, Heinrich
Author_Institution :
IBM Almaden Res. Center, San Jose, CA, USA
fDate :
5/1/1991 12:00:00 AM
Abstract :
The Viterbi algorithm (VA) is considered as an example of a fairly complex algorithm that needs to be implemented for high-speed applications. A brief introduction to the algorithm is given, and the state of the art of high-speed Viterbi decoders is reviewed. The three principal levels of introducing additional parallelism into an algorithm-bit level, word level, and algorithm level-are outlined, and a solution for the VA at the bit level is indicated.<>
Keywords :
VLSI; decoding; parallel algorithms; parallel architectures; VLSI architecture; Viterbi algorithm; algorithm level; bit level; high-speed Viterbi decoders; parallel Viterbi decoding; parallel algorithm; word level; Application specific integrated circuits; CMOS logic circuits; CMOS technology; Clocks; Decoding; Frequency; Gallium arsenide; Pipeline processing; Signal processing algorithms; Viterbi algorithm;
Journal_Title :
Communications Magazine, IEEE
