Branch effect reduction techniques

Author

Uht, Augustus K. ; Sindagi, Vijay ; Somanathan, Sajee

Author_Institution

Rhode Island Univ., USA

Volume

30

Issue

5

fYear

1997

fDate

5/1/1997 12:00:00 AM

Firstpage

71

Lastpage

81

Abstract

Branch effects are the biggest obstacle to gaining significant speedups when running general purpose code on instruction level parallel machines. The article presents a survey which compares current branch effect reduction techniques, offering hope for greater gains. We believe this survey is timely because research is bearing much fruit: speedups of 10 or more are being demonstrated in research simulations and may be realized in hardware within a few years. The hardware required for large scale exploitation is great, but the density of transistors per chip is increasing exponentially, with estimates of 50 to 100 million transistors per chip by the year 2000

Keywords

computational complexity; parallel architectures; parallel machines; parallel programming; software performance evaluation; branch effect reduction techniques; general purpose code; instruction level parallel machines; large scale exploitation; research simulations; transistor density; transistors per chip; Application software; Concurrent computing; Counting circuits; Data flow computing; Hardware; Instruments; Large-scale systems; Parallel machines; Parallel processing; Uncertainty;

fLanguage

English

Journal_Title

Computer

Publisher

ieee

ISSN

0018-9162

Type

jour

DOI

10.1109/2.589913

Filename

589913