A new circuit optimization technique for high performance CMOS circuits

A novel transistor sizing technique with a concise problem formulation and rigorous optimization scheme is described. A circuit optimization technique for high-performance CMOS circuits is presented for proper balance of chip speed and area. The timing specification is accommodated as a design constraint, and reliability issues in the charge sharing and noise margin, which have been neglected in previous optimization tools, are also embedded into the design constraints. The optimization scheme used in this approach does not require derivatives, and therefore, can be used for a broad class of continuous cost functions. Special attention is given to the most effective use of silicon area based on the sensitivity of the delay time with respect to the transistor size. Excessively large transistor sizes are avoided by using the resource redistribution scheme. This timing allocation scheme allows the computation time to be linearly proportional to the number of gates