DocumentCode :
1249897
Title :
Wringing maximum performance from delay lines
Author :
Fitzsimmons, Dennis
Author_Institution :
Eng. Components Co., San Luis Obispo, CA, USA
Volume :
15
Issue :
5
fYear :
1999
fDate :
9/1/1999 12:00:00 AM
Firstpage :
52
Lastpage :
54
Abstract :
The subtleties of designing and specifying delay lines into specific circuit applications can be somewhat confusing. In order to help electronic engineers extract the maximum performance from these components, here are 10 important considerations to which design and specifying engineers can refer in order to ensure the optimal incorporation of delay lines into their circuits. Just as important, the following pointers can help avoid any missed delivery dates because of an application error
Keywords :
circuit CAD; circuit optimisation; delay lines; circuit CAD; delay lines; optimal incorporation; specific circuit applications; CMOS logic circuits; Capacitance; Clocks; Contacts; Delay lines; Design engineering; Engineering profession; Frequency; Impedance; Space vector pulse width modulation;
fLanguage :
English
Journal_Title :
Circuits and Devices Magazine, IEEE
Publisher :
ieee
ISSN :
8755-3996
Type :
jour
DOI :
10.1109/101.795093
Filename :
795093
Link To Document :
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