Title :
Concurrent event handling through multithreading
Author :
Keckler, Stephen W. ; Chang, Andrea ; Chatterjee, W.S.L.S. ; Dally, William J.
Author_Institution :
Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
Abstract :
Exceptions have traditionally been used to handle infrequently occurring and unpredictable events during normal program execution. Current trends in microprocessor and operating systems design continue to increase the cost of event handling. Because of the deep pipelines and wide out-of-order superscalar architectures of contemporary microprocessors, an event may need to nullify a large number of in-flight instructions. Large register files require existing software systems to save and restore a substantial amount of process state before executing an exception handler. At the same time, processors are executing in environments that supply higher event frequencies and demand higher performance. We have developed an alternative architecture, "concurrent event handling", that incorporates multithreading into event handling architectures. Instead of handling the event in the faulting thread\´s architectural and pipeline registers, the fault handler is forked into its own thread slot and executes concurrently with the faulting thread. Microbenchmark programs show a factor-of-3 speedup for concurrent event handling over a traditional architecture on code that takes frequent exceptions. We also demonstrate substantial speedups on two event-based applications. Concurrent event handling is implemented in the MIT\´s MAP (Multi-ALU Processor) chip.
Keywords :
exception handling; interrupts; multi-threading; parallel architectures; MAP chip; MIT multi-ALU processor chip; concurrent event handling; context switching; deep pipelines; event frequency; event handling architectures; event-based applications; exception handling; fault handler forking; infrequently occurring events; instruction nullification; interrupts; microbenchmark programs; microprocessor design; multithreading; operating systems design; performance; process state restoration; register files; speedup; thread slot; unpredictable events; wide out-of-order superscalar architectures; Computer architecture; Costs; Microprocessors; Multithreading; Operating systems; Out of order; Pipelines; Registers; Software systems;
Journal_Title :
Computers, IEEE Transactions on