DocumentCode
1250185
Title
Partial scan with preselected scan signals
Author
Pan, Peichen ; Liu, C.L.
Author_Institution
Dept. of Electr. & Comput. Eng., Clarkson Univ., Potsdam, NY, USA
Volume
48
Issue
9
fYear
1999
fDate
9/1/1999 12:00:00 AM
Firstpage
1000
Lastpage
1005
Abstract
This paper deals with partial scan approaches that select scan signals oblivious to the availability of flip-flops (FFs). Such approaches can greatly reduce the number of scan signals since maximum freedom is presented when selecting signals. However, to actually scan the selected signals, one must make them drive FFs. We study the problem of replicating and retiming a circuit to make a set of scan signals drive FFs while preserving the set of cycles broken by the signals. We present a framework for solving the problem. Based on the framework, we present an efficient algorithm which also minimizes the amount of logic replication
Keywords
design for testability; logic design; logic testing; flip-flops; logic replication; partial scan; preselected scan signals; retiming; scan signals; Circuit faults; Circuit testing; Design for testability; Feedback loop; Flip-flops; Iterative algorithms; Logic gates; Sequential analysis; Sequential circuits; Wires;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.795228
Filename
795228
Link To Document