Performance evaluation of a high-speed ATM switch with multiple common memories

We consider a common-memory (CM) type N × N ATM switch, where CM block consists of K (K ⩾ N) separated submemories. We propose an address assignment algorithm to avoid input/output contentions so that we can have the read/write speed of submemories as low as the interface (input/output) port speed. Taking a replication-at-sending approach to multicast, we pursue memory efficiency and maximum throughput. We develop an analytical model to evaluate the system in terms of cell loss ratio and average delay time. In the analysis, we take into account two loss factors causing losses of incoming cells: (1) the failure of scheduling to avoid the input/output contentions and (2) overflow in the CM block. The first factor is dominating and can be significantly reduced by increasing K. From our analytical results compared with simulations, it is observed that we can take K ≈ 3N as a guide of system design