• DocumentCode
    1251847
  • Title

    Searching networks with unrestricted edge costs

  • Author

    Dasgupta, Parthasarathi ; Sen, Anup K. ; Nandy, Subhas C. ; Bhattacharya, Bhargab B.

  • Author_Institution
    Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
  • Volume
    31
  • Issue
    6
  • fYear
    2001
  • fDate
    11/1/2001 12:00:00 AM
  • Firstpage
    497
  • Lastpage
    507
  • Abstract
    Best-first and depth-first heuristic search algorithms often assume underlying search graphs with only nonnegative edge costs and attempt to optimize simple objective functions. Applicability of these algorithms to graphs with both positive and negative edge costs is not completely studied. In the paper, two new problems are identified: one in computational geometry and the other in the layout design of very large scale integrated (VLSI) circuits. The former problem relates to a weight-balanced bipartitioning of a given set of points in a plane. The goal of the second problem is to find an area-balanced staircase path in a VLSI floorplan. Formulations of these problems lead to an interesting directed acyclic search graph with positive, zero and negative edge costs and an objective function of general nature. These problems are NP-hard. To solve such general problems optimally, search schemes are proposed. Experimental results reveal the efficacy and versatility of the proposed schemes, the depth-first scheme being the better choice. It is shown that the classical number-partitioning problem can also be formulated in this framework
  • Keywords
    VLSI; computational complexity; computational geometry; directed graphs; integrated circuit layout; tree searching; NP-hard problems; VLSI circuits; VLSI floorplan; area-balanced staircase path; best-first heuristic search algorithms; computational geometry; depth-first heuristic search algorithms; directed acyclic search graph; layout design; search graphs; unrestricted edge costs; very large scale integrated circuits; weight-balanced bipartitioning; Circuits; Computational geometry; Computational intelligence; Computer science; Cost function; Heuristic algorithms; Intersymbol interference; Partitioning algorithms; Shortest path problem; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Systems, Man and Cybernetics, Part A: Systems and Humans, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1083-4427
  • Type

    jour

  • DOI
    10.1109/3468.983405
  • Filename
    983405