Title :
Impact of gate induced drain leakage on overall leakage of submicrometer CMOS VLSI circuits
Author :
Semenov, Oleg ; Pradzynski, Andrzej ; Sachdev, Manoj
Author_Institution :
Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
fDate :
2/1/2002 12:00:00 AM
Abstract :
In this paper, the impact of gate induced drain leakage (GIDL) on the overall leakage of submicrometer VLSI circuits is studied. GIDL constitutes a serious constraint, with regards to off-state current, in scaled down complimentary metal-oxide-semiconductor (CMOS) devices for DRAM and/or EEPROM applications. Our research shows that the GIDL current is also a serious problem in scaled CMOS digital VLSI circuits. We present the experimental and simulation data of GIDL current as a function of 0.35-μm CMOS technology parameters and layout of CMOS standard cells. The obtained results show that a poorly designed standard cell library for VLSI application may result in extremely high leakage current and poor yield
Keywords :
CMOS memory circuits; DRAM chips; EPROM; VLSI; circuit CAD; circuit simulation; integrated circuit design; integrated circuit testing; integrated circuit yield; leakage currents; 0.35 micron; CMOS IC reliability; CMOS VLSI circuits; CMOS layout; CMOS standard cells; CMOS technology parameters; DRAM applications; EEPROM applications; GIDL; GIDL constraint; GIDL current; VLSI; VLSI circuits; VLSI yield; band-to-band tunneling; downscaled CMOS devices; gate induced drain leakage; leakage current; off-state current; scaled CMOS digital VLSI circuits; simulation data; standard cell library; CMOS logic circuits; CMOS technology; Circuit simulation; Degradation; EPROM; Leakage current; Random access memory; Testing; Tunneling; Very large scale integration;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
