Design and analysis of high-speed random access memory with Coulomb blockade charge confinement

Author

Katayama, Kozo ; Mizuta, Hiroshi ; Müller, Heinz-Olaf ; Williams, David ; Nakazato, Kazuo

Author_Institution

Central Res. Lab., Hitachi Ltd., Kokubunji, Japan

Volume

46

Issue

11

fYear

1999

fDate

11/1/1999 12:00:00 AM

Firstpage

2210

Lastpage

2216

Abstract

A silicon-based memory cell utilizing Coulomb blockade is analyzed for use as a high-speed RAM. Operation principles and design guidelines are given by simple analytical modeling and simulations. By performing transient waveform Monte Carlo simulations, high-speed write operation is demonstrated with a time shorter than 10 ns. The memory node voltage of less than 0.1 V is detected by a newly proposed split-gate cell structure with a minimum disturbance to/from nonselected cells, which indicates the compatibility of this structure with conventional field effect transistors

Keywords

Coulomb blockade; Monte Carlo methods; high-speed integrated circuits; integrated circuit modelling; quantum interference devices; random-access storage; 10 ns; Coulomb blockade charge confinement; Monte Carlo simulation; Si; analytical model; design; field effect transistor; high-speed random access memory; lateral single electron memory; split-gate cell; Analytical models; Capacitors; Electrons; Flash memory; Laboratories; Memory architecture; Nanocrystals; Random access memory; Read-write memory; Voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.796298

Filename

796298