DocumentCode
1252610
Title
Throughput advantages of asynchronous prober control
Author
Powers, Robert J.
Volume
5
Issue
3
fYear
1988
fDate
6/1/1988 12:00:00 AM
Firstpage
56
Lastpage
63
Abstract
Parallel testing of memories at the wafer-sort stage can offer significant throughput advantages. Accepted methods at this state involve synchronous prober control. A model is presented that shows how asynchronous prober control can increase throughput 36% over that possible with synchronous control.<>
Keywords
integrated circuit testing; integrated memory circuits; asynchronous prober control; memory testing; parallel testing; wafer-sort stage; Costs; Flowcharts; Indexing; Needles; Packaging; Power generation economics; Probes; Semiconductor device modeling; Software testing; Throughput;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/54.7963
Filename
7963
Link To Document