Design of a clock synchronisation sub-system for parallel embedded systems

Software tools are being developed to support a design methodology specific to parallel real-time continuous-dataflow embedded systems. The authors describe the design of a global clock sub-system which is an essential component of an event trace tool. A new amalgam of algorithms is proposed which attends to the trade-off between clock accuracy and the need to restrict disturbance of the application whilst recording traces. The details of an implementation on a hybrid parallel processor, as well as the results of tracing applications in the given problem domain, are included