e6500: Freescale´s Low-Power, High-Performance Multithreaded Embedded Processor

Author

Burgess, David ; Gieske, Edmund ; Holt, James ; Hoy, Thomas ; Whisenhunt, Gary

Author_Institution

Freescale Semicond., Austin, TX, USA

Volume

32

Issue

5

fYear

2012

Firstpage

26

Lastpage

36

Abstract

Freescale´s e6500 targets highly efficient scalable embedded processing. It incorporates many architectural and microarchitectural performance innovations, from advanced virtualization technologies and judicious hardware thread resource allocation to coherency and interconnect transaction avoidance techniques, including decorated storage operations, lightweight ordering barriers, and cache stashing. Power-efficiency techniques, including cascading system power management and automatic execution unit powering, are coupled with a power-optimized physical design.

Keywords

cache storage; embedded systems; multi-threading; multiprocessing systems; power aware computing; resource allocation; virtualisation; Freescale e6500 processor; architectural performance innovation; automatic execution unit powering; cache stashing; cascading system power management; decorated storage operation; embedded processing; hardware thread resource allocation; lightweight ordering barrier; microarchitectural performance innovation; multithreaded embedded processor; power-efficiency technique; power-optimized physical design; transaction avoidance technique; virtualization technology; Embedded systems; Instruction sets; Microarchitecture; Program processors; Scalability; System-on-a-chip; Technological innovation; Freescale; e6500; embedded; low-power; multithreading; processor;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/MM.2012.55

Filename

6253195