Predicting potential performance for digital circuits

Author

Chen, Chunhong ; Yang, Xiaojian ; Sarraftadeh, M.

Author_Institution

Comput. Sci. Dept., Windsor Univ., Ont., Canada

Volume

21

Issue

3

fYear

2002

fDate

3/1/2002 12:00:00 AM

Firstpage

253

Lastpage

262

Abstract

Presents a new concept of potential slack to measure so-called potential performance of digital circuits. Potential means how much improvement could be made in the future in terms of timing, area, and power dissipation. Predicting potential performance helps the circuit designers make good design decisions at a specific level of abstraction. The authors describe two algorithms for potential slack: an optimal algorithm and a fast greedy algorithm. The former is based on a maximal-independent set on transitive graphs, while the latter focuses on potential slack estimation in a greedy manner. Applications to gate- and physical-level design problems are provided to show the effectiveness of potential slack in predicting the potential performance of digital circuits

Keywords

circuit CAD; circuit optimisation; digital integrated circuits; graph theory; integrated circuit design; low-power electronics; timing; area; design decisions; digital circuits; fast greedy algorithm; maximal-independent set; optimal algorithm; physical-level design problems; potential slack; power dissipation; timing; transitive graphs; Circuit synthesis; Computer science; Costs; Delay; Design optimization; Digital circuits; Greedy algorithms; Integrated circuit measurements; Power dissipation; Timing;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.986420

Filename

986420