• DocumentCode
    1254647
  • Title

    Provably good global buffering by generalized multiterminal multicommodity flow approximation

  • Author

    Dragan, Feodor F. ; Kahng, Andrew B. ; Mandoiu, Ion I. ; Muddu, Sudhakar ; Zelikovsk, Alexander

  • Author_Institution
    Dept. of Math. & Comput. Sci., Kent State Univ., OH, USA
  • Volume
    21
  • Issue
    3
  • fYear
    2002
  • fDate
    3/1/2002 12:00:00 AM
  • Firstpage
    263
  • Lastpage
    274
  • Abstract
    To implement high-performance global interconnect without impacting the placement and performance of existing blocks, the use of buffer blocks is becoming increasingly popular in structured-custom and block-based application specified integrated circuit methodologies. We address the problem of how to perform the buffering of global multiterminal nets given an existing buffer block plan. We give provably good and heuristic algorithms for this problem. The method routes connections using available buffer blocks, such that required upper and lower bounds on buffer intervals are satisfied. In addition, the algorithms allow more than one buffer to be inserted into any given connection and observe upper bounds and parity constraints on the number of buffers per connection. Most importantly, and unlike previous works on the problem, we take into account: 1) multiterminal nets; 2) multiple routing layers; 3) simultaneous buffered routing and compaction; and 4) buffer libraries. Our method outperforms existing algorithms for the problem, based on two-pin decompositions of the nets, and has been validated on top-level layouts extracted from a recent high-end microprocessor design
  • Keywords
    buffer circuits; circuit layout CAD; integrated circuit design; integrated circuit interconnections; logic CAD; microprocessor chips; multiterminal networks; network routing; software libraries; block-based application specified integrated circuit; buffer block planning; buffer blocks; buffer intervals; buffer libraries; global interconnect; global multiterminal nets; heuristic algorithms; high-end microprocessor design; multiple routing layers; parity constraints; provably good global buffering; simultaneous buffered routing; structured-custom integrated circuit methodologies; top-level layouts; two-pin decompositions; upper bounds; Application specific integrated circuits; Compaction; Computer science; Heuristic algorithms; Integrated circuit interconnections; Libraries; Repeaters; Research and development; Routing; Upper bound;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.986421
  • Filename
    986421