• DocumentCode
    1254675
  • Title

    Wire width planning for interconnect performance optimization

  • Author

    Cong, Jason ; Pan, Zhigang

  • Author_Institution
    Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
  • Volume
    21
  • Issue
    3
  • fYear
    2002
  • fDate
    3/1/2002 12:00:00 AM
  • Firstpage
    319
  • Lastpage
    329
  • Abstract
    In this paper, we study wire width planning for interconnect performance optimization in an interconnect-centric design flow. We first propose some simplified, yet near-optimal wire sizing schemes, using only one or two discrete wire widths. Our sensitivity study on wire sizing optimization further suggests that there exists a small set of "globally" optimal wire widths for a range of interconnects. We develop general and efficient methods for computing such a "globally" optimal wire width design and show rather surprisingly that using only two "predesigned" widths for each metal layer, we are still able to achieve close to optimal performance compared with that by using many possible widths, not only for one fixed length, but also for all wire lengths assigned at each metal layer. Our wire width planning can consider different design objectives and wire length distributions. Moreover, our method has a predictable small amount of errors compared with optimal solutions. We expect that our simplified wire sizing schemes and wire width planning methodology will be very useful for better design convergence and simpler routing architectures
  • Keywords
    VLSI; circuit CAD; circuit optimisation; integrated circuit design; integrated circuit interconnections; VLSI; design convergence; interconnect performance optimization; interconnect-centric design flow; metal layer; near-optimal wire sizing; optimal wire width; routing architectures; sizing optimization; wire planning; wire width planning; Capacitance; Circuit optimization; Costs; Delay; Design optimization; Integrated circuit interconnections; Integrated circuit reliability; Routing; Very large scale integration; Wire;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.986425
  • Filename
    986425