DC Compact Model for SOI Tunnel Field-Effect Transistors

A physics-based dc compact model for SOI tunnel field-effect transistors (TFETs) has been developed in this paper utilizing Landauer approach. The important transistor electrical parameters, i.e., threshold voltage V_th, charge in the channel Q, gate capacitance C_G, drain current I_DS, subthreshold swing S, transconductance g_m, and output conductance g_DS, have been modeled. The model predicts the low subthreshold swing values (less than 60 mV/dec) observed in TFETs and shows a good match with the technology computer aided design (TCAD) results. Model validation was carried out using TCAD simulation for different TFET structures with abrupt junctions, i.e., 40-nm Si nTFET and pTFET, a 0.4-μm Si nTFET, and a 40-nm Ge nTFET. The compact model predictions are in good agreement with the TCAD simulation results.