DocumentCode :
1254796
Title :
An expert system to automate timing design
Author :
Kara, A. ; Rastogi, Raw ; Kawamura, Kazuhiko
Author_Institution :
NEC Corp., Tokyo, Japan
Volume :
5
Issue :
5
fYear :
1988
Firstpage :
28
Lastpage :
40
Abstract :
Presents a novel approach for automating the timing design of interfaces between VLSI chips in microcomputer systems. The Prolog-based expert system, called TDS (for timing design system), incorporates the heuristic knowledge of the hardware designer. TDS is a rule-based system that interprets the specification sheets of VLSI chips and can synthesize, diagnose, and verify timing charts at the expert´s level. The system uses a functional model based on timing specifications, not the structural information. TDS can model other interfaces that are based on timing specifications, such as standard bus interfaces.<>
Keywords :
computer interfaces; expert systems; logic CAD; TDS; VLSI chips; expert system; heuristic knowledge; interfaces; microcomputer systems; rule-based system; timing charts; timing design; timing design system; timing specifications; Algorithm design and analysis; Circuit analysis; Circuit simulation; Circuit synthesis; Design automation; Digital systems; Expert systems; Hardware; Timing; Very large scale integration;
fLanguage :
English
Journal_Title :
Design & Test of Computers, IEEE
Publisher :
ieee
ISSN :
0740-7475
Type :
jour
DOI :
10.1109/54.7980
Filename :
7980
Link To Document :
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