Designing for high-level test generation

Recent work has shown that test generation complexity and test set size can be reduced by high-level analysis that exploits the natural design hierarchy found in digital circuits. A design modification approach aimed at facilitating high-level testing by enhancing circuit regularity is proposed. This approach can improve the testability of a broad class of useful array- and tree-like circuits, including counters, decoders, and arithmetic logic units (ALUs). This is demonstrated for the specific case of decoders and decoding trees, where the test set size is reduced from O(2ⁿ) to O(n). A systematic design technique called level separation (LS) is presented for generalized tree circuits, which are useful for fast implementation of arithmetic functions like addition and multiplication. Design for testability (DFT) and hierarchical test generation are shown to reduce the test size from O(n) to O(log₂ n) for such circuits. A case study of a 16-b four-function ALU is presented to illustrate the utility of the LS method