DocumentCode
1254949
Title
Systolic array implementation of a decimator and an interpolator
Author
Kwan, H.K. ; Okullo-Oballa, T.S.
Author_Institution
Dept. of Electr. & Electron. Eng., Hong Kong Univ., Hong Kong
Volume
135
Issue
1
fYear
1988
fDate
1/1/1988 12:00:00 AM
Firstpage
70
Lastpage
72
Abstract
Two systolic arrays for the VLSI implementation of the decimation and interpolating structures advanced by Valenzuela and Constantinides are presented. Each of the resultant arrays consists of basic cells characterised by nearest neighbour interconnections and high throughput rate.
Keywords
VLSI; cellular arrays; digital filters; signal processing; VLSI implementation; decimator; interpolator; nearest neighbour interconnections; systolic array implementation;
fLanguage
English
Journal_Title
Computers and Digital Techniques, IEE Proceedings E
Publisher
iet
ISSN
0143-7062
Type
jour
Filename
6512
Link To Document