Microprocessor Soft Error Rate Prediction Based on Cache Memory Analysis

Static raw soft-error rates (SER) of COTS microprocessors are classically obtained with particle accelerators, but they are far larger than real application failure rates that depend on the dynamic application behavior and on the cache protection mechanisms. In this paper, we propose a new methodology to evaluate the real cache sensitivity for a given application, and to calculate a more accurate failure rate. This methodology is based on the monitoring of cache accesses, and requires a microprocessor simulator. It is applied in this paper to the LEON3 soft-core with several benchmarks. Results are validated by fault injections on one implementation of the processor running the same programs: the proposed tool predicted all errors with only a small over-estimation.