Memory efficient programmable processor chip for inverse Haar transform

Author

Ruiz, G.A. ; Michell, J.A.

Author_Institution

Dept. de Electron. y Computadores, Facultad de Ciencias, Santander, Spain

Volume

46

Issue

1

fYear

1998

fDate

1/1/1998 12:00:00 AM

Firstpage

263

Lastpage

268

Abstract

In this correspondence, a processor chip programmable between N=8 and N=1024 for the unidimensional inverse Haar transform (1-D-IFHT) is presented. The processor uses a low latency data-flow with an architecture that minimizes the internal memory and an adder/subtracter as the only computing element. The control logic has a single and modular structure and can be easily extended to longer transforms. A prototype of the 1-D-IFHT processor has been implemented using a standard-cell design methodology and a 1.0-μm CMOS process on a 11.7 mm² die. The maximum data rate is close to 60 MHz

Keywords

CMOS digital integrated circuits; VLSI; digital signal processing chips; integrated circuit layout; inverse problems; transforms; 1-D-IFHT; 1.0 micron; 1.0-μm CMOS process; 60 MHz; adder/subtracter; architecture; computing element; control logic; internal memory; inverse Haar transform; low latency data-flow; maximum data rate; memory efficient programmable processor chip; prototype; single modular structure; standard-cell design methodology; CMOS logic circuits; CMOS process; CMOS technology; Computer architecture; Delay; Image coding; Prototypes; Transform coding; Very large scale integration; Wavelet transforms;

fLanguage

English

Journal_Title

Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1053-587X

Type

jour

DOI

10.1109/78.651233

Filename

651233