DocumentCode
1255119
Title
Corner-parasitics-free low-cost trench isolation
Author
Schwalke, U. ; Gabric, Z. ; Elbel, N. ; Bothe, K. ; Hadawi, D. ; Janssen, I. ; Schon, P. ; Inioutis, A. ; Klose, R. ; Plagmann, J.
Author_Institution
Infineon Technol. AG, Munich, Germany
Volume
20
Issue
11
fYear
1999
Firstpage
563
Lastpage
565
Abstract
In this work, we present results on a novel low-cost, corner-parasitics-free trench isolation process. Regarding process complexity, this approach is almost as simple as LOGOS isolation, since the isolation oxide is deposited selectively within the trench. Due to the self-planarizing nature of the fill oxide, the global planarization sequence is largely simplified. With respect to scalability, this approach offers all the advantages of trench isolation with its abrupt transition of active area to isolation. However, in contrast to previous trench isolation schemes, corner-parasitic effects are eliminated by means of the extended trench isolation gate technology (EXTIGATE) device geometry. As a result, excellent narrow width characteristics and subthreshold curves without kink effect are obtained.
Keywords
CMOS integrated circuits; isolation technology; 0.25 micron; CMOS IC fabrication; EXTIGATE device geometry; corner-parasitics-free trench isolation; extended trench isolation gate technology; global planarization sequence; isolation oxide; low-cost trench isolation; narrow width characteristics; scalability; subthreshold curves; Degradation; Etching; Geometry; Isolation technology; Lithography; Oxidation; Planarization; Scalability; Silicon; Topology;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/55.798044
Filename
798044
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