A comparison of analog and digital circuit implementations of low power matched filters for use in portable wireless communication terminals

In this paper, analog and digital circuit realizations of a parallel programmable matched filter are examined. Through wide variations of the design space parameters, the general trend that is observed is that short, fast circuits tend to favor an analog implementation, while longer, slower circuits make a digital implementation more appropriate. A methodology is provided for choosing the preferable circuit-implementing technology when power consumption-as a function of data precision, filter length, operating frequency, technology scaling, and the maturity of the fabrication process-is used as the primary metric of comparison. It is shown that neither the analog nor the digital matched filter implementation is universally more power efficient than the other. Rather, a surface is mapped in the multidimensional design space where, on one side of this surface, a digital solution is preferable, while on the other side of the surface, an analog circuit is appropriate. Equations are given which delineate the position of this transitional surface in terms of the design space parameters, and example calculations and plots depicting the regions of dominance for the digital and analog matched filters for specific process and system parameters are presented