DocumentCode
1255493
Title
Design of low-power high-speed bipolar frequency dividers
Author
Alioto, M. ; Di Cataldo, G. ; Palumbo, G.
Author_Institution
Dipt. Elettrico Elettronico e Sistemistico, Catania Univ., Italy
Volume
38
Issue
4
fYear
2002
fDate
2/14/2002 12:00:00 AM
Firstpage
158
Lastpage
160
Abstract
A low-power current mode bipolar frequency divider is discussed. Low-power consumption is achieved owing to the design strategy being based on a progressive reduction of bias currents through stages without affecting divider operation speed. The strategy is independent of the process used and simple to design, avoiding the trial-and-error approach based on simulations
Keywords
bipolar logic circuits; current-mode circuits; current-mode logic; flip-flops; frequency dividers; high-speed integrated circuits; low-power electronics; D-latch delay; SPICE simulations; bias currents; bipolar current mode logic; current mode bipolar frequency divider; design strategy; level shifters; low-power consumption; minimum delay; optimum design; optimum latch current; progressive reduction; successive stage design;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20020104
Filename
986839
Link To Document