The implementation of the new type impedance measurement system

The design principle and implementation scheme of a new type FPGA-based RLC impedance analyzer within the scope of 100Hz~100kHz is designed. The system adopts FPGA and DA framework to realize the DDS signal output with low distortion, takes DA of multiplication type as phase sensitive detector, uses the orthogonal decomposition method to decompose the measured signals into orthogonal component and in-phase component to raise the signal-to-noise ratio, and uses the dual slope integral circuit with zero crossing compensation as signal acquisition circuit to make the acquired signal to be the quotient between orthogonal component and in-phase component, which greatly decrease the drift error of the electric circuit. The experiment verified that the system index can reach 0.1%.