Exact reliability analysis of combinational logic circuits

Author

Dokouzgiannis, Stavros P. ; Kontoleon, John M.

Author_Institution

Dept. of Electr. Eng., Thessaloniki Univ., Greece

Volume

37

Issue

5

fYear

1988

fDate

12/1/1988 12:00:00 AM

Firstpage

493

Lastpage

500

Abstract

A novel method is presented for the exact reliability analysis of combinational logic circuits. A model is developed that allows the logic circuit to be presented by a circuit equivalent graph (CEG). The reliability is analyzed by a systematic searching of certain subgraphs from the CEG. A computer algorithm and an example are given. The method gives the exact solution to the combinational logic circuit reliability-analysis problem. This is achieved by proper gate/circuit modeling, which allows the enumeration of all redundant fault vectors in a given circuit. Due to the concept of dominance among fault vectors, the number of necessary enumerations is appreciably reduced, and thus circuits with a few tens of gates can be efficiently analyzed

Keywords

circuit reliability; combinatorial circuits; graph theory; circuit equivalent graph; combinational logic circuits; computer algorithm; exact reliability analysis; gate/circuit modeling; model; redundant fault vectors; subgraphs; Boolean algebra; Circuit faults; Combinational circuits; Feeds; Joining processes; Logic circuits; Logic gates; Reliability theory;

fLanguage

English

Journal_Title

Reliability, IEEE Transactions on

Publisher

ieee

ISSN

0018-9529

Type

jour

DOI

10.1109/24.9870

Filename

9870