Title :
Reliability Evaluation for Single Event Transients on Digital Circuits
Author :
Liu, Baojun ; Cai, Li
Author_Institution :
Dept. of Electron. Sci. & Technol., Air Force Eng. Univ., Xi´´An, China
Abstract :
The effect of single event transient (SET) on reliability has become a significant concern for digital circuits. This paper proposed an algorithm for evaluating the reliability for SET on digital circuits, based on signal probability, universal generating function technique, and generalized reliability block diagrams. The algorithm provides an expression for the reliability of SET under consideration for the effects of logic masking, error attenuation of gates, and crosstalk effects among interconnect wires. We perform simulations of ISCAS85 circuits. The results indicate that the proposed algorithm can effectively evaluate the reliability for SET on circuits. The error attenuation of gates can increase the reliability by more than 41.6%, and the masking and crosstalk effects will improve the reliability by more than 43%.
Keywords :
circuit simulation; crosstalk; integrated circuit interconnections; integrated circuit reliability; integrated logic circuits; logic gates; wires (electric); ISCAS85 circuit simulation; SET; crosstalk effect; digital IC; digital integrated circuit; gate error attenuation; interconnect wire; logic masking effect; reliability block diagram; signal probability; single event transient; universal generating function technique; Crosstalk; Digital circuits; Integrated circuit modeling; Integrated circuit reliability; Logic gates; Transient analysis; Crosstalk effects; masking; reliability evaluation; single event transient;
Journal_Title :
Reliability, IEEE Transactions on
DOI :
10.1109/TR.2012.2209249
