Title :
A low-power 8-PAM serial transceiver in 0.5-μm digital CMOS
Author :
Foley, David J. ; Flynn, Michael P.
Author_Institution :
Parthus Technol., Dublin, Ireland
fDate :
3/1/2002 12:00:00 AM
Abstract :
An 8-PAM CMOS transceiver is described in this paper. Pre-emphasis is implemented without an increase in DAC resolution or digital computation. The receiver oversamples with three fully differential 3-bit ADCs. The prototype transmits at up to 1.3 Gb/s and has a measured bit error rate of less than 1 in 1013 for an 810-Mb/s pseudorandom bit sequence transmission. The device, packaged in a 68-pin ceramic leadless chip carrier, is implemented in 0.5-μm digital CMOS, occupies 2 mm2, and dissipates 400 mW from a 3.3-V supply
Keywords :
CMOS digital integrated circuits; low-power electronics; pulse amplitude modulation; transceivers; 0.5 micron; 1.3 Gbit/s; 3 bit; 3.3 V; 400 mW; 810 Mbit/s; ADC; DAC; bit error rate; ceramic leadless chip carrier package; digital CMOS; low-power 8-PAM serial transceiver; pseudorandom bit sequence transmission; Bit error rate; Circuits; Clocks; Delay; Frequency; Packaging; Semiconductor device measurement; Synthesizers; Transceivers; Transmitters;
Journal_Title :
Solid-State Circuits, IEEE Journal of
