A "digital" 6-bit ADC in 0.25-μm CMOS

Author

Donovan, Conor ; Flynn, Michael P.

Author_Institution

Dept. of Microelectron., Nat. Univ. of Ireland, Cork, Ireland

Volume

37

Issue

3

fYear

2002

fDate

3/1/2002 12:00:00 AM

Firstpage

432

Lastpage

437

Abstract

Traditionally, circuit designers have adopted analog techniques to overcome comparator offset in flash converters. These schemes have an adverse effect on area and power consumption and, more seriously, do not scale easily to low-voltage processes. We describe a digital technique which removes the accuracy constraints from the comparators. With no analog matching requirements, the comparators can be small, fast, and power efficient. A 6-bit prototype converter built in a standard 0.25-μm digital CMOS process occupies 1.2 mm² and dissipates 150 mW from a 2.2-V supply at 400 MS/s

Keywords

CMOS integrated circuits; analogue-digital conversion; comparators (circuits); integrated circuit design; low-power electronics; mixed analogue-digital integrated circuits; 0.25 micron; 150 mW; 2.2 V; 6 bit; CMOS 6-bit ADC; comparator offset; digital CMOS process; digital calibration; digital technique; flash converters; low-voltage processes; mixed-mode ICs; mixed-signal applications; power consumption; power dissipation; power efficient comparators; trip-point distribution; CMOS technology; Calibration; Capacitors; Decoding; Digital circuits; Digital signal processing; Linearity; Microelectronics; Redundancy; Resistors;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.987096

Filename

987096