An Opto-electrical NoC with Traffic Flow Prediction in Chip Multiprocessors

Network-on-Chip (NoC) paradigm has emerged as a revolutionary methodology to integrate numerous IP blocks on a single chip. The achievable performance of adopting NoCs is constrained by the performance limitation mainly imposed by the metal wires that are the physical realization of communication channels. According to the International Technology Roadmap for Semiconductors (ITRS) report, new interconnect paradigms providing huge bandwidth is in need for future products. The current wired channels have limited bandwidth, and consequently, they limit the performance enhancements that NoC architectures can provide. Optical interconnects are capable of achieving better performance via high-speed high-bandwidth point-to-point connections, if their cost overhead can be mitigated. In this paper, we evaluate the performance of opto-electrical multistage NoC architectures which use a sample-based flow prediction method at hardware level with minimum communication and area overhead to predict heavily communicating flows. Our evaluation of the proposed structure demonstrates its superior functionality in terms of throughput, latency, and energy dissipation with respect to traditional NoC architectures.