Thermal stresses in multilayer ceramic capacitors: numerical simulations

Author

Scott, Geoffrey C. ; Astfalk, Greg

Author_Institution

AT&T Bell Lab., Princeton, NJ, USA

Volume

13

Issue

4

fYear

1990

fDate

12/1/1990 12:00:00 AM

Firstpage

1135

Lastpage

1145

Abstract

Numerical simulations using a previously published model (see G.C. Scott and G. Astfolk, ASME J. Electron. Pack., vol.112, p.35-40, 1989) to characterize the development of thermal stresses in surface-mounted multilayer ceramic capacitors (MLCCs) are discussed. The model was used to investigate the effect of several important factors on the development of thermal stresses in MLCCs. These factors relate to the solder process temperature profile and to the MLCC printed wiring board geometry and material properties. The results indicate that the peak temperature during wave solder and the geometry and material properties of the MLCC termination have a major influence on the development of thermal stresses in MLCCs. These factors are actually a small portion of the factors commonly thought to have a significant influence on thermal stress development

Keywords

capacitors; ceramics; printed circuits; soldering; surface mount technology; thermal stress cracking; thermal stresses; printed wiring board geometry; solder process temperature profile; surface-mounted multilayer ceramic capacitors; thermal stress cracking; thermal stresses; wave solder peak temperature; Capacitors; Ceramics; Electrons; Geometry; Material properties; Nonhomogeneous media; Numerical simulation; Temperature; Thermal factors; Thermal stresses;

fLanguage

English

Journal_Title

Components, Hybrids, and Manufacturing Technology, IEEE Transactions on

Publisher

ieee

ISSN

0148-6411

Type

jour

DOI

10.1109/33.62564

Filename

62564