Title :
On the SiO2-based gate-dielectric scaling limit for low-standby power applications in the context of a 0.13 μm CMOS logic technology
Author :
Lin, Yo-Sheng ; Huang, Huan-Tsung ; Wu, Chung-Cheng ; Leung, Ying-Keung ; Pan, Hsu-Yang ; Chang, Tse-En ; Chen, Wei-Ming ; Liaw, Jung-Jih ; Diaz, Carlos H.
fDate :
3/1/2002 12:00:00 AM
Abstract :
This paper describes a leading-edge 0.13 μm low-leakage CMOS logic technology. To achieve competitive off-state leakage current (I off) and gate delay (Td) performance at operating voltages (Vcc) of 1.5 V and 1.2 V, devices with 0.11 μm nominal gate length (Lg-nom) and various gate-oxide thicknesses (Tox) were fabricated and studied. The results show that low power and memory applications are limited to oxides not thinner than 21.4 Å in order to keep acceptable off-state power consumption at Vcc=1.2 V. Specifically, two different device designs are introduced here. One design named LP (Tox=26 Å) is targeted for Vcc=1.5 V with worst case Ioff <10 pA/μm and nominal gate delay 24 ps/gate. Another design, named LP1 (Tox=22 Å) is targeted for Vcc =1.2 V with worst case Ioff<20 pA/μm and nominal gate delay 27 ps/gate. This work demonstrates n/pMOSFETs with excellent 520/210 and 390/160 μA/μm nominal drive currents at Vcc for LP and LP1, respectively. Process capability for low-power applications is demonstrated using a CMOS 6T-SRAM with 2.43 μm2 cell size. In addition, intrinsic gate-oxide TDDB tests of LP1 (T ox=22 Å) demonstrate that gate oxide reliability far exceeding 10 years is achieved for both n/pMOSFETs at T=125°C and V cc=1.5 V
Keywords :
CMOS logic circuits; CMOS memory circuits; MOSFET; SRAM chips; delays; dielectric thin films; electric breakdown; integrated circuit design; integrated circuit reliability; integrated circuit testing; leakage currents; logic design; logic testing; low-power electronics; silicon compounds; 0.11 micron; 0.13 micron; 1.2 V; 1.5 V; 10 year; 125 C; 21.4 angstrom; 22 angstrom; 24 ps; 26 angstrom; 27 ps; CMOS 6T-SRAM; CMOS logic technology; SiO2-Si; SiO2-based gate-dielectric scaling limit; cell size; device designs; drive currents; gate delay; gate oxide reliability; gate-oxide thickness; intrinsic gate-oxide TDDB tests; low power applications; low-leakage CMOS logic technology; low-standby power applications; memory applications; nMOSFETs; nominal gate delay; nominal gate length; off-state leakage current; off-state power consumption; operating voltages; pMOSFETs; CMOS logic circuits; CMOS process; CMOS technology; Delay; Energy consumption; Leakage current; Logic devices; MOSFETs; Testing; Voltage;
Journal_Title :
Electron Devices, IEEE Transactions on
