Advanced model and analysis of series resistance for CMOS scaling into nanometer regime. II. Quantitative analysis

Author

Kim, Seong-Dong ; Park, Cheol-Min ; Woo, Jason C S

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA

Volume

49

Issue

3

fYear

2002

fDate

3/1/2002 12:00:00 AM

Firstpage

467

Lastpage

472

Abstract

Source/drain (S/D) series resistance components and device/process parameters contributing to series resistance are extensively analyzed using advanced model for future CMOS design and technology scaling into the nanometer regime. The total series resistance of a device is found to be very sensitive to the variations of the sidewall thickness, the doping concentration in the deep junction region, and the Schottky barrier height of the silicide contact. A prediction of series resistance trends with technology generation indicates that silicide-diffusion contact resistance and overlap resistance will be major components in the total series resistance of nanometer-scale CMOS transistors scaled according to the ITRS roadmap. The key factors for challenging scaling barriers related to parasitic resistance are quantitatively examined as a function of technology scaling and it is shown that the series resistance can be substantially reduced through controlling both the abruptness of the S/D junction profile and the silicide Schottky barrier engineering

Keywords

CMOS integrated circuits; Schottky barriers; contact resistance; electric resistance; electrical contacts; integrated circuit design; integrated circuit interconnections; integrated circuit metallisation; integrated circuit modelling; nanotechnology; CMOS design scaling; CMOS scaling; CMOS technology scaling; ITRS roadmap; S/D junction profile abruptness; S/D series resistance; Schottky barrier height; deep junction region; doping concentration; model; nanometer regime; nanometer-scale CMOS transistors; overlap resistance; parasitic resistance; scaling barriers; series resistance; sidewall thickness; silicide Schottky barrier engineering; silicide contact; silicide-diffusion contact resistance; source/drain series resistance; technology scaling; total series resistance; CMOS process; CMOS technology; Contact resistance; Doping; Electric resistance; Nanoscale devices; Schottky barriers; Semiconductor device modeling; Semiconductor process modeling; Silicides;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.987118

Filename

987118