A 40-GHz Fast-Locked All-Digital Phase-Locked Loop Using a Modified Bang-Bang Algorithm

Author

Hung, Chao-Ching ; Liu, Shen-Iuan

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

58

Issue

6

fYear

2011

fDate

6/1/2011 12:00:00 AM

Firstpage

321

Lastpage

325

Abstract

A 40-GHz fast-locked all-digital phase-locked loop (ADPLL) using a modified bang-bang algorithm is presented. An inductor is used to extend the frequency tuning range of a 40-GHz digitally controlled oscillator. This ADPLL is fabricated by a 90-nm complementary metal-oxide-semiconductor process. The measured peak-to-peak jitter and the root-mean-square jitter are 2.622 ps and 303.632 fs, respectively, at 40 GHz. The measured locked times are 1.3 ms and 15 μs without and with the modified bang-bang algorithm, respectively.

Keywords

CMOS integrated circuits; digital phase locked loops; field effect MMIC; inductors; jitter; millimetre wave oscillators; complementary metal-oxide-semiconductor process; digitally controlled oscillator; fast-locked all-digital phase-locked loop; frequency 40 GHz; frequency tuning range; modified bang-bang algorithm; peak-to-peak jitter; root-mean-square jitter; size 90 nm; Arrays; Clocks; Inductors; Jitter; Oscillators; Phase locked loops; Varactors; All digital; digitally controlled oscillator (DCO); fast locked; phase-locked loop (PLL);

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2011.2149610

Filename

5928394