Title :
An experimental 1-Mbit CMOS SRAM with configurable organization and operation
Author :
Williams, Tyson ; Beilstein, K. ; El-Kareh ; Flaker, R. ; Gravenites, Gregory ; Lipa, Robert ; Lee, Hsing-San ; Maslack, Joseph ; Pessetto, John ; Pokorny, William F. ; Roberge, Michael ; Zeller, Harold
Author_Institution :
IBM, Essex Junction, VT, USA
fDate :
10/1/1988 12:00:00 AM
Abstract :
A 1-Mb SRAM (static random-access memory) configurable as a 128-kb×8, 256-kb×4, or 1-Mb×1 memory featuring asynchronous operation with static-column and chip-enable-access speedup modes or synchronous operation with a fast-page (toggle) or static-column mode is described. It has been fabricated in a double-metal, double-polysilicon CMOS process with 0.7-μm geometry and special SRAM structures. The measured synchronous access of 29 ns with a fast-page mode access of 22 ns. Measured asynchronous access is 34 ns with a static-column access of 33 ns and a chip-select speedup access of 29 ns. The SRAMs six-transistor CMOS memory cell is 58.24 μm2
Keywords :
CMOS integrated circuits; integrated memory circuits; random-access storage; 0.7 micron; 1 Mbit; 22 to 34 ns; CMOS SRAM; Si; asynchronous operation; chip-enable-access speedup modes; configurable organization; double poly-Si process; double-metal; double-polysilicon; fast-page mode access; six transistor memory cell; static RAM; static random-access memory; static-column mode; synchronous operation; toggle mode; Buffer storage; CMOS process; Cache storage; Circuit testing; Decoding; Military computing; Packaging; Random access memory; Semiconductor device measurement; Solid state circuits;
Journal_Title :
Solid-State Circuits, IEEE Journal of
