Title :
A Novel Five-Photomask Low-Temperature Polycrystalline Silicon CMOS Structure for AMLCD Application
Author :
Lee, Sang-Jin ; Lee, Seok-Woo ; Oh, Kum-Mi ; Park, Soo-Jeong ; Lee, Kyung-Eon ; Yoo, Yong-Su ; Lim, Kyoung-Moon ; Yang, Myoung-Su ; Yang, Yong-Suk ; Hwang, Yong-Kee
Author_Institution :
LG Display R&D Center, Paju, South Korea
Abstract :
A novel five-mask low-temperature polycrystalline silicon (LTPS) CMOS structure was verified by manufacturing the thin-film transistor test samples using the proposed five-mask LTPS CMOS process. In integrating the five-mask CMOS structure, a selective contact barrier metal formation process was developed, without additional photomask steps, to solve the issue of high-contact-resistance problem encountered inevitably in the contact between the indium tin oxide and doped polycrystalline silicon (poly-Si) source-drain layers. The five-mask CMOS technology was also confirmed by manufacturing a five-mask CMOS panel for the active-matrix liquid-crystal-display application.
Keywords :
contact resistance; cryogenic electronics; elemental semiconductors; liquid crystal displays; masks; semiconductor device manufacture; silicon; thin film transistors; AMLCD; Si; active-matrix liquid crystal display; five photomask low-temperature polycrystalline silicon CMOS structure; five-mask LTPS CMOS process; high contact resistance problem; selective contact barrier metal formation process; source-drain layers; thin-film transistor test sample manufacturing; Active matrix liquid crystal displays; Active matrix technology; CMOS integrated circuits; CMOS process; CMOS technology; Capacitors; Costs; Indium tin oxide; Logic gates; MOS devices; Metals; Silicon; Testing; Thin film transistors; Active-matrix liquid crystal display (AMLCD); complementary metal–oxide–semiconductor (CMOS); low-temperature polycrystalline silicon (LTPS); thin-film transistor (TFT);
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2010.2053868
