DocumentCode
1257350
Title
Protocol wrappers for layered network packet processing in reconfigurable hardware
Author
Braun, Florian ; Lockwood, John ; Waldvogel, Marcel
Author_Institution
Stuttgart Univ., Germany
Volume
22
Issue
1
fYear
2002
Firstpage
66
Lastpage
74
Abstract
A library of layered protocol wrappers processes Internet packets in reconfigurable hardware. Collectively, the wrappers simplify and streamline the implementation of high-level networking functions by abstracting the operation of lower-level packet processing functions. The library synthesizes into field-programmable gate array (FPGA) logic and is utilized in a network platform called the field-programmable port extender (FPX). The library processes asynchronous transfer mode (ATM) cells, ATM adaptation layer 5 (AAL5) frames, Internet protocol (IP) messages, and user datagrarn protocol (UDP) packets directly in hardware. Applications can process data at several layers of the protocol stack using the library of wrappers discussed in this article. Layers are important for networks because they let applications abstract from above and below details of the network protocols. At the lowest layer, networks modify raw data passing between interfaces. At higher levels, the applications process variable length frames or IP packets.A network platform called the field-programmable port extender (FPX) streamlines and simplifies network transmission processing directly in hardware
Keywords
computer networks; protocols; reconfigurable architectures; FPX; Internet packets; high-level networking functions; layered protocol wrappers; networking platform; protocol stack; reconfigurable hardware; Asynchronous transfer mode; Field programmable gate arrays; Hardware; Internet; Libraries; Logic arrays; Logic gates; Network synthesis; Protocols; Reconfigurable logic;
fLanguage
English
Journal_Title
Micro, IEEE
Publisher
ieee
ISSN
0272-1732
Type
jour
DOI
10.1109/40.988691
Filename
988691
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