Models for systematic design and verification of frequency synthesizers

Recently, much effort has been put on the integration of telecommunication front-ends. For a semiconductor company to follow the large market request in shortening the time-to-market constraint for new products, a systematic design methodology has to be followed, starting from a top-down design followed by a bottom-up verification. This paper provides, in models, each of these design phases for the example of frequency synthesizers. During the design phase, fast models are needed to explore the design space. On the other hand, accurate nonlinear models are derived for the verification phase to simulate complex specifications, e.g., the oscillator´s output phase noise. An illustration of these models is based on the design of a 1.8 GHz CMOS frequency synthesizer